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T6K01
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
T6K01
COLUMN DRIVER LSI FOR A DOT MATRIX GRAPHIC LCD
The T6K01 is a column (segment) driver for a dot matrix graphic LCD. The T6K01 offers low power consumption, due to the CMOS Si-Gate process. It is designed to interface directly with a microprocessor unit (MPU). A program running on the MPU can drive the T6K01 asynchronously. The T6K01 stores data transferred from the MPU in its built-in RAM. The data stored in the built-in display RAM corresponds to the image on the LCD screen; the data is converted into the LCD drive signal. A configuration of two T6K01s and one T6C03 can be used to drive a 480 x 160-dot LCD.
Features
l Dot matrix graphic LCD column driver with display RAM l Display RAM capacity: 160 lines x 240 outputs = 38400 bits l LCD drive output: 240 l Interface: 8-bit MPU l Relation between RAM data and display RAM bit data = 1 display ON RAM bit data = 0 display OFF l Display OFF function l Low power consumption l Logic power supply: 2.7 to 3.3 V l LCD power supply: 8.0 to 26.0 V l CMOS Process l Package: TCP (Tape Carrier Package)
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T6K01
Block Diagram
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T6K01
Pin Assignment
Note: The above diagram shows the pin configuration of the LSI chip; it does not show the configuration of the tape carrier package.
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Pin Functions
Pin Name SEG1 to SEG240 CL FP FR DB0 to DB7 AD0 to AD12 R/W Pin No. 46 to 285 10 11 12 13 to 20 21 to 33 34 I/O Output Input Input Input I/O Input Input Column driver outputs Shift clock pulse Display synchronous signal Frame signal Data bus Address bus Read / write select R / W = H Read selected R / W = L Write selected Chip enable Data write: Data write enabled on rising edge of / CE Data read: Data read out while / CE is at L level Display off. Usually connected to VDD. / DSPOF = H: Display-on mode. (SEG1 to SEG240) are operational. / DSPOF = L: Display-off mode. (SEG1 to SEG240) are at the VSS level. Reset signal: / RST = L Reset state Data direction select Test pin. Usually connected to VDD Power supply Functions
/ CE
35
Input
/ DSPOF / RST DIR / TEST1, 2 VDD, VSS VCCL, VCCR VLC0L, VLC0R VLC2L, VLC2R VLC3L, VLC3R VLC5L, VLC5R HVSSL, HVSSR
36 37 38 8, 9 7, 39 1, 45 2, 44 3, 43 4, 42 5, 41 6, 40
Input Input Input Input
Power supply for LCD drive
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Function of Each Block
RAM cell
The RAM capacity is 160 lines x 240 outputs for a total of 38400 bits.
DIR
This circuit changes the data flow direction and page selection sequence.
Address decoder
This decoder selects one RAM address for read / write operation.
8-bit counter + decoder
The decoder selects one RAM cell from the 160 address lines for display operation.
Latch
The data is latched from the display RAM on the falling edge of CL.
Column driver circuit and LCD voltage generation circuit
The T6K01 has 240 column drivers and four different LCD drive output voltage levels. The display data from the latch circuit and the M signal determine which of the four LCD drive voltages is selected. This circuit is shown in the following diagram.
Relation Between FR, Data Input and Output Level
/ DSPOF L H H H H FR * L L H H Input Data (RAM Data) * L H L H Output Level VSS / VLC5 VLC3 VSS / VLC5 VLC2 VLC0
*: INVALID
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The relation between DIR and the memory map
(1) DIR = H
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(2) DIR = L
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Absolute Maximum Ratings (Ta = 25C)
Item Supply Voltage (1) Supply Voltage (2) Input Voltage Operating Temperature Storage Temperature Symbol VDD (Note 2) (Note 1, 2) VIN (Note 2, 3) Topr Tstg Rating -0.3 to 6.5 -0.3 to 28.0 -0.3 to VDD +0.3 -20 to 75 -55 to 125 Unit V V V C C
Note 1: Note 2: Note 3: Note 4:
VCCL, VCCR, VLC0L, VLC0R, VLC2L, VLC2R, VLC3L, VLC3R, VLC5L and VLC5R Referenced to VSS, HVSSL and HVSSR Applies to all data bus and I / O pins. Ensure that the following condition is always maintained. VCCL / R VLC0L / R VLC2L / R VLC3L / R V LC5L / R HVSSL / R
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T6K01
Electrical Characteristics DC Characteristics Test Conditions
(Unless Otherwise Noted, VSS = 0 V, VDD = 3.0 V 10%, VCCL / R = 23.0 V 10%, Ta = -20 to 75C)
Item Operating Supply (1) Operating Supply (2) H Level Input Voltage Symbol VDD VCC VIH Test Circuit Test Condition Min 2.7 8.0 0.7 VDD Typ. Max 3.3 26.0 VDD Unit V V V Pin Name VDD VCCL, VCCR DB0 to DB7 AD0 to AD7, / RST, / DSPOF, / CE, R / W, D / I, CL, FP, FR, DIR, / TEST
L Level
VIL
0
0.3 VDD
V
Output Voltage
H Level L Level
VOH VOL Rcol

IOH = -400 A IOL = 400 A Load current = 100 A (Note 4)
VDD -0.4 VSS

VDD 0.4 3.0
V DB0 to DB7 V k SEG1 to SEG160 DB0 to DB7 AD0 to AD7, / RST, / DSPOF, / CE, R / W, D / I, CL, FP, FR, DIR, / TEST CL VSS, HVSSL, HVSSR, VLC5L, VLC5R VSS, HVSSL, HVSSR, VLC5L, VLC5R VSS, HVSSL, HVSSR, VLC5L, VLC5R
Column Driver Output Resistance
Input Leakage
IIL
VIN = VDD to VSS
-1
1
A
Operating Freq. Current Consumption (1) Current Consumption (2) Current Consumption (3)
fCL ISS1

(Note 1)
10
410
50 520
kHz A
ISS2
(Note 2)
45
65
A
ISS3
(Note 3)
-1
1
A
Note 1: Current consumption while internal data receiver is operating VDD = 3.0 V 10%, VCCL / R = 23.0 V, Ta = 25C, 1 / 13 bias, 1 / 160 duty, no load, fFP = 70 Hz, f / CE = 5 MHz Note 2: Current consumption while internal data receiver is sleeping VDD = 3.0 V 10%, VCCL / R = 23.0 V, Ta = 25C, 1 / 13 bias, 1 / 160 duty, no load, fFP = 70 Hz, f / CE = 0 Hz Note 3: Standby current consumption VDD = 3.0 V 10%, VCCL / R = 23.0 V, Ta = 25C, no load, fFP = 0 Hz, f / CE = 0 Hz Note 4: VCCL / R = VLC0L / R = 23.0 V, VLC2L / R = VCC x 11 / 13, VLC3L / R = VCC x 2 / 13, HVSSL / R = VLC5L / R = 0 V
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AC Characteristics (1)
Test Conditions (Unless Otherwise Noted, VSS = 0 V, VDD = 3.0 V 10%, Ta = -20 to 75C)
Item Enable Cycle Time Enable Pulse Width Enable Rise / Fall Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Data Delay Time Data Hold Time Symbol tcycE PWEH tEr, tEf tAS tAH tDS tDHW tDD (Note) tDHR (Note) Min 250 160 0 10 100 20 20 Max 20 180 Unit ns ns ns ns ns ns ns ns ns
Load Circuit
Note: With load circuit connected
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AC Characteristics (2)
display data
Test Conditions (Unless Otherwise Noted, VSS = 0 V, VDD = 3.0 V 10%, Ta = -20 to 75C)
Item CL Pulse Width H CL Pulse Width L CL Rise / Fall Time FP Set-up Time FP Hold Time Symbol tCWH tCWL tr, tf tFSU tFHD Pin Name CL CL CL FP FP Min 500 500 100 100 Max 50 Unit ns ns ns ns ns
AC Characteristics (3)
Item CL-to-FP-margin time FP-to-CL-margin time
Symbol tCF tFC
Condition
Min 20 0
Max
Unit ns ns
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Application Circuit
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RESTRICTIONS ON PRODUCT USE
000707EBE
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * Polyimide base film is hard and thin. Be careful not to injure yourself on the film or to scratch any other parts with the film. Try to design and manufacture products so that there is no chance of users touching the film after assembly, or if they do , that there is no chance of them injuring themselves. When cutting out the film, try to ensure that the film shavings do not cause accidents. After use, treat the leftover film and reel spacers as industrial waste. * Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases this can cause the device to malfunction. This is especially true for devices in which the surface (back), or side of the chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. Exposure to light both during regular operation and during inspection must be taken into account. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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